level-triggered interrupt

См. также в других словарях:

• Interrupt — This article is about computer interrupts. For the study of the effect of disruptions on job performance, see Interruption science. In computing, an interrupt is an asynchronous signal indicating the need for attention or a synchronous event in… …   Wikipedia

• Interrupt priority level — The interrupt priority level (IPL) is a part of the current system interrupt state, which indicates the interrupt requests that will currently be accepted. The IPL may be indicated in hardware by the registers in a Programmable Interrupt… …   Wikipedia

• Interrupt handler — An interrupt handler, also known as an interrupt service routine (ISR), is a callback subroutine in an operating system or device driver whose execution is triggered by the reception of an interrupt. Interrupt handlers have a multitude of… …   Wikipedia

• Programmable Interrupt Controller — A Programmable Interrupt Controller (PIC) is a device which allows priority levels to be assigned to its interrupt outputs. When the device has multiple interrupt outputs to assert, it will assert them in the order of their relative priority.… …   Wikipedia

• Transport triggered architecture — The transport triggered architecture (TTA) is an application specific instruction set processor ( ASIP ) architecture template that allows easy customization of microprocessor designs. The basic idea of transport triggering is to allow programs… …   Wikipedia

• прерывание от уровня с запоминанием — Сигнал (импульсного) прерывания по приоритетному уровню, запоминаемому с помощью триггера. [Е.С.Алексеев, А.А.Мячев. Англо русский толковый словарь по системотехнике ЭВМ. Москва 1993] Тематики информационные технологии в целом EN level triggered… …   Справочник технического переводчика

• Intel 8259 — The Intel 8259 is a family of Programmable Interrupt Controllers (PICs) designed and developed for use with the Intel 8085 and Intel 8086 8 bit and 16 bit microprocessors. The family originally consisted of the 8259, 8259A, and 8259B PICs, though …   Wikipedia

• Immunity Aware Programming — When writing firmware for an embedded system, immunity aware programming is a set of programming techniques used in an attempt to tolerate transient errors in the program counter or other that would otherwise lead to failure.Immunity aware… …   Wikipedia

• Conventional PCI — PCI Local Bus Three 5 volt 32 bit PCI expansion slots on a motherboard (PC bracket on left side) …   Wikipedia

• Peripheral Component Interconnect — Infobox Computer Hardware Bus name = PCI fullname = peripheral component interconnection caption = Five 5V 32 bit PCI expansion slots on a motherboard invent date = July 1993 invent name = Intel super date = 2004 super name = PCI Express width =… …   Wikipedia

• C10k problem — Le c10k problem[note 1] que l on pourrait traduire en français par le problème des dix mille connexions simultanées, est un code numérique utilisé pour exprimer la limitation que la plupart des serveurs ont en termes de connexions réseaux. Cette… …   Wikipédia en Français